### Equations

********** Mapped Logic **********
$OpTx$$OpTx$FX_DC$1_INV$9 <= (ja22 AND jd(14).PIN);
FDCPE_bstate0: FDCPE port map (bstate(0),'0','0',bstate_CLR(0),bstate_PRE(0)); bstate_CLR(0) <= (NOT jd(9).PIN AND NOT jd(8).PIN AND NOT jd(7).PIN AND NOT jd(15).PIN AND NOT jd(13).PIN AND NOT jd(12).PIN AND NOT jd(11).PIN AND NOT jd(10).PIN AND NOT jd(5).PIN AND NOT jd(3).PIN AND ja22 AND NOT jd(6).PIN AND NOT jd(4).PIN AND NOT jrw AND NOT jrom1 AND NOT jd(0).PIN AND jd(14).PIN); bstate_PRE(0) <= (NOT jd(9).PIN AND NOT jd(8).PIN AND NOT jd(7).PIN AND NOT jd(15).PIN AND NOT jd(13).PIN AND NOT jd(12).PIN AND NOT jd(11).PIN AND NOT jd(10).PIN AND NOT jd(5).PIN AND NOT jd(3).PIN AND ja22 AND NOT jd(6).PIN AND NOT jd(4).PIN AND NOT jrw AND NOT jrom1 AND jd(0).PIN AND jd(14).PIN);
FDCPE_bstate1: FDCPE port map (bstate(1),'0','0',bstate_CLR(1),bstate_PRE(1)); bstate_CLR(1) <= (NOT jd(9).PIN AND NOT jd(8).PIN AND NOT jd(7).PIN AND NOT jd(15).PIN AND NOT jd(13).PIN AND NOT jd(12).PIN AND NOT jd(11).PIN AND NOT jd(10).PIN AND NOT jd(5).PIN AND NOT jd(3).PIN AND ja22 AND NOT jd(6).PIN AND NOT jd(4).PIN AND NOT jrw AND NOT jd(1).PIN AND NOT jrom1 AND jd(14).PIN); bstate_PRE(1) <= (NOT jd(9).PIN AND NOT jd(8).PIN AND NOT jd(7).PIN AND NOT jd(15).PIN AND NOT jd(13).PIN AND NOT jd(12).PIN AND NOT jd(11).PIN AND NOT jd(10).PIN AND NOT jd(5).PIN AND NOT jd(3).PIN AND ja22 AND NOT jd(6).PIN AND NOT jd(4).PIN AND NOT jrw AND jd(1).PIN AND NOT jrom1 AND jd(14).PIN);
FDCPE_bstate2: FDCPE port map (bstate(2),'0','0',bstate_CLR(2),bstate_PRE(2)); bstate_CLR(2) <= (NOT jd(9).PIN AND NOT jd(8).PIN AND NOT jd(7).PIN AND NOT jd(15).PIN AND NOT jd(13).PIN AND NOT jd(12).PIN AND NOT jd(11).PIN AND NOT jd(10).PIN AND NOT jd(5).PIN AND NOT jd(3).PIN AND NOT jd(2).PIN AND ja22 AND NOT jd(6).PIN AND NOT jd(4).PIN AND NOT jrw AND NOT jrom1 AND jd(14).PIN); bstate_PRE(2) <= (NOT jd(9).PIN AND NOT jd(8).PIN AND NOT jd(7).PIN AND NOT jd(15).PIN AND NOT jd(13).PIN AND NOT jd(12).PIN AND NOT jd(11).PIN AND NOT jd(10).PIN AND NOT jd(5).PIN AND NOT jd(3).PIN AND jd(2).PIN AND ja22 AND NOT jd(6).PIN AND NOT jd(4).PIN AND NOT jrw AND NOT jrom1 AND jd(14).PIN);
eza0 <= ((NOT ja22 AND bstate(0)) OR (jrom1 AND bstate(0)));
eza1 <= ((NOT ja22 AND bstate(1)) OR (jrom1 AND bstate(1)) OR (ja22 AND NOT jrw AND NOT jrom1));
ezrd30 <= NOT (((ja22 AND jrw AND NOT jrom1) OR (jrw AND NOT jrom1 AND bstate(2)) OR (bstate(2) AND bstate(1) AND NOT bstate(0))));
ezwr31 <= NOT (((bstate(2) AND bstate(1) AND NOT bstate(0)) OR (ja22 AND NOT jrw AND NOT jrom1 AND NOT jd(14).PIN) OR (NOT ja22 AND NOT jrw AND NOT jrom1 AND bstate(2))));
floe <= NOT ((NOT ja22 AND jrw AND NOT jrom1 AND NOT bstate(2) AND NOT bstate(1)));
flwe <= NOT ((NOT ja22 AND NOT jrw AND NOT jrom1 AND NOT bstate(2) AND NOT bstate(1) AND NOT bstate(0)));
FDCPE_ireset0: FDCPE port map (ireset0,'0','0',ireset0_CLR,ireset0_PRE); ireset0_CLR <= (jd(9).PIN AND jd(8).PIN AND jd(7).PIN AND NOT jd(15).PIN AND jd(13).PIN AND jd(12).PIN AND jd(11).PIN AND NOT jd(10).PIN AND jd(5).PIN AND jd(3).PIN AND jd(2).PIN AND ja22 AND NOT jd(6).PIN AND NOT jd(4).PIN AND NOT jrw AND NOT jd(1).PIN AND NOT jrom1 AND NOT jd(0).PIN AND jd(14).PIN); ireset0_PRE <= (jd(9).PIN AND jd(8).PIN AND jd(7).PIN AND NOT jd(15).PIN AND jd(13).PIN AND jd(12).PIN AND jd(11).PIN AND NOT jd(10).PIN AND jd(5).PIN AND jd(3).PIN AND jd(2).PIN AND ja22 AND NOT jd(6).PIN AND NOT jd(4).PIN AND NOT jrw AND NOT jd(1).PIN AND NOT jrom1 AND jd(0).PIN AND jd(14).PIN);
jd_I(0) <= pd(0).PIN; jd(0) <= jd_I(0) when jd_OE(0) = '1' else 'Z'; jd_OE(0) <= (jrw AND NOT jrom1);
jd_I(1) <= pd(1).PIN; jd(1) <= jd_I(1) when jd_OE(1) = '1' else 'Z'; jd_OE(1) <= (jrw AND NOT jrom1);
jd_I(2) <= pd(2).PIN; jd(2) <= jd_I(2) when jd_OE(2) = '1' else 'Z'; jd_OE(2) <= (jrw AND NOT jrom1);
jd_I(3) <= pd(3).PIN; jd(3) <= jd_I(3) when jd_OE(3) = '1' else 'Z'; jd_OE(3) <= (jrw AND NOT jrom1);
jd_I(4) <= pd(4).PIN; jd(4) <= jd_I(4) when jd_OE(4) = '1' else 'Z'; jd_OE(4) <= (jrw AND NOT jrom1);
jd_I(5) <= pd(5).PIN; jd(5) <= jd_I(5) when jd_OE(5) = '1' else 'Z'; jd_OE(5) <= (jrw AND NOT jrom1);
jd_I(6) <= pd(6).PIN; jd(6) <= jd_I(6) when jd_OE(6) = '1' else 'Z'; jd_OE(6) <= (jrw AND NOT jrom1);
jd_I(7) <= pd(7).PIN; jd(7) <= jd_I(7) when jd_OE(7) = '1' else 'Z'; jd_OE(7) <= (jrw AND NOT jrom1);
jd_I(8) <= pd(8).PIN; jd(8) <= jd_I(8) when jd_OE(8) = '1' else 'Z'; jd_OE(8) <= (jrw AND NOT jrom1);
jd_I(9) <= pd(9).PIN; jd(9) <= jd_I(9) when jd_OE(9) = '1' else 'Z'; jd_OE(9) <= (jrw AND NOT jrom1);
jd_I(10) <= pd(10).PIN; jd(10) <= jd_I(10) when jd_OE(10) = '1' else 'Z'; jd_OE(10) <= (jrw AND NOT jrom1);
jd_I(11) <= pd(11).PIN; jd(11) <= jd_I(11) when jd_OE(11) = '1' else 'Z'; jd_OE(11) <= (jrw AND NOT jrom1);
jd_I(12) <= pd(12).PIN; jd(12) <= jd_I(12) when jd_OE(12) = '1' else 'Z'; jd_OE(12) <= (jrw AND NOT jrom1);
jd_I(13) <= pd(13).PIN; jd(13) <= jd_I(13) when jd_OE(13) = '1' else 'Z'; jd_OE(13) <= (jrw AND NOT jrom1);
jd_I(14) <= pd(14).PIN; jd(14) <= jd_I(14) when jd_OE(14) = '1' else 'Z'; jd_OE(14) <= (jrw AND NOT jrom1);
jd_I(15) <= pd(15).PIN; jd(15) <= jd_I(15) when jd_OE(15) = '1' else 'Z'; jd_OE(15) <= (jrw AND NOT jrom1);
pd_I(0) <= jd(0).PIN; pd(0) <= pd_I(0) when pd_OE(0) = '1' else 'Z'; pd_OE(0) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);
pd_I(1) <= jd(1).PIN; pd(1) <= pd_I(1) when pd_OE(1) = '1' else 'Z'; pd_OE(1) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);
pd_I(2) <= jd(2).PIN; pd(2) <= pd_I(2) when pd_OE(2) = '1' else 'Z'; pd_OE(2) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);
pd_I(3) <= jd(3).PIN; pd(3) <= pd_I(3) when pd_OE(3) = '1' else 'Z'; pd_OE(3) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);
pd_I(4) <= jd(4).PIN; pd(4) <= pd_I(4) when pd_OE(4) = '1' else 'Z'; pd_OE(4) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);
pd_I(5) <= jd(5).PIN; pd(5) <= pd_I(5) when pd_OE(5) = '1' else 'Z'; pd_OE(5) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);
pd_I(6) <= jd(6).PIN; pd(6) <= pd_I(6) when pd_OE(6) = '1' else 'Z'; pd_OE(6) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);
pd_I(7) <= jd(7).PIN; pd(7) <= pd_I(7) when pd_OE(7) = '1' else 'Z'; pd_OE(7) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);
pd_I(8) <= jd(8).PIN; pd(8) <= pd_I(8) when pd_OE(8) = '1' else 'Z'; pd_OE(8) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);
pd_I(9) <= jd(9).PIN; pd(9) <= pd_I(9) when pd_OE(9) = '1' else 'Z'; pd_OE(9) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);
pd_I(10) <= jd(10).PIN; pd(10) <= pd_I(10) when pd_OE(10) = '1' else 'Z'; pd_OE(10) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);
pd_I(11) <= jd(11).PIN; pd(11) <= pd_I(11) when pd_OE(11) = '1' else 'Z'; pd_OE(11) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);
pd_I(12) <= jd(12).PIN; pd(12) <= pd_I(12) when pd_OE(12) = '1' else 'Z'; pd_OE(12) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);
pd_I(13) <= jd(13).PIN; pd(13) <= pd_I(13) when pd_OE(13) = '1' else 'Z'; pd_OE(13) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);
pd_I(14) <= jd(14).PIN; pd(14) <= pd_I(14) when pd_OE(14) = '1' else 'Z'; pd_OE(14) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);
pd_I(15) <= jd(15).PIN; pd(15) <= pd_I(15) when pd_OE(15) = '1' else 'Z'; pd_OE(15) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);
preset <= ((ireset0) OR (NOT ja22 AND jrw AND NOT jrom1));
Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE);