    cpldfit:  version J.37                              Xilinx Inc.
                                      Fitter Report
    Design Name: main                                Date:  8- 8-2007,  4:36PM
    Device Used: XC9572XL-10-VQ64
    Fitting Status: Successful

    *************************  Mapped Resource Summary  **************************

    Macrocells     Product Terms    Function Block   Registers      Pins
    Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot
    44 /72  ( 61%) 88  /360  ( 24%) 64 /216 ( 30%)   4  /72  (  6%) 42 /52  ( 81%)

    ** Function Block Resources **

    Function    Mcells      FB Inps     Pterms      IO
    Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot
    FB1          10/18       13/54       23/90      10/13
    FB2           9/18       12/54       18/90       9/13
    FB3          13/18       22/54       25/90       9/14
    FB4          12/18       17/54       22/90      11/12
                 -----       -----       -----      -----
                 44/72       64/216      88/360     39/52

    * - Resource is exhausted

    ** Global Control Resources **

    Global clock net(s) unused.
    Global output enable net(s) unused.
    Global set/reset net(s) unused.

    ** Pin Resources **

    Signal Type    Required     Mapped  |  Pin Type            Used    Total
    ------------------------------------|------------------------------------
    Input         :    3           3    |  I/O              :    39      46
    Output        :    7           7    |  GCK/IO           :     1       3
    Bidirectional :   32          32    |  GTS/IO           :     1       2
    GCK           :    0           0    |  GSR/IO           :     1       1
    GTS           :    0           0    |
    GSR           :    0           0    |
                     ----        ----
            Total     42          42

    ** Power Data **

    There are 0 macrocells in high performance mode (MCHP).
    There are 44 macrocells in low power mode (MCLP).
    End of Mapped Resource Summary
    *************************  Summary of Mapped Logic  ************************

    ** 39 Outputs **

    Signal                     Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
    Name                       Pts   Inps          No.  Type    Use     Mode Rate State
    pd<10>                     2     4     FB1_2   8~   I/O     I/O     LOW  SLOW
    pd<14>                     2     4     FB1_3   12~  I/O     I/O     LOW  SLOW
    pd<15>                     2     4     FB1_4   13~  I/O     I/O     LOW  SLOW
    pd<11>                     2     4     FB1_5   9~   I/O     I/O     LOW  SLOW
    pd<12>                     2     4     FB1_6   10~  I/O     I/O     LOW  SLOW
    pd<13>                     2     4     FB1_8   11~  I/O     I/O     LOW  SLOW
    eza0                       2     3     FB1_9   15~  GCK/I/O O       LOW  SLOW
    eza1                       3     4     FB1_10  18~  I/O     O       LOW  SLOW
    ezwr31                     3     7     FB1_15  19~  I/O     O       LOW  SLOW
    ezrd30                     3     6     FB1_17  20~  I/O     O       LOW  SLOW
    jd<10>                     2     3     FB2_2   60~  I/O     I/O     LOW  SLOW
    jd<2>                      2     3     FB2_3   58~  I/O     I/O     LOW  SLOW
    jd<5>                      2     3     FB2_4   59~  I/O     I/O     LOW  SLOW
    jd<12>                     2     3     FB2_5   61~  I/O     I/O     LOW  SLOW
    jd<3>                      2     3     FB2_6   62~  I/O     I/O     LOW  SLOW
    jd<4>                      2     3     FB2_8   63~  I/O     I/O     LOW  SLOW
    jd<11>                     2     3     FB2_9   64~  GSR/I/O I/O     LOW  SLOW
    pd<8>                      2     4     FB2_12  4~   I/O     I/O     LOW  SLOW
    pd<9>                      2     4     FB2_14  5~   GTS/I/O I/O     LOW  SLOW
    pd<6>                      2     4     FB3_3   31~  I/O     I/O     LOW  SLOW
    pd<7>                      2     4     FB3_4   32~  I/O     I/O     LOW  SLOW
    pd<3>                      2     4     FB3_6   34~  I/O     I/O     LOW  SLOW
    pd<2>                      2     4     FB3_10  39~  I/O     I/O     LOW  SLOW
    pd<1>                      2     4     FB3_11  33~  I/O     I/O     LOW  SLOW
    pd<0>                      2     4     FB3_12  40~  I/O     I/O     LOW  SLOW
    pd<5>                      2     4     FB3_14  35~  I/O     I/O     LOW  SLOW
    floe                       1     5     FB3_16  42~  I/O     O       LOW  SLOW
    pd<4>                      2     4     FB3_17  38~  I/O     I/O     LOW  SLOW
    preset                     2     4     FB4_2   43~  I/O     O       LOW  SLOW
    jd<15>                     2     3     FB4_3   46~  I/O     I/O     LOW  SLOW
    jd<0>                      2     3     FB4_4   47~  I/O     I/O     LOW  SLOW
    flwe                       1     6     FB4_5   44~  I/O     O       LOW  SLOW
    jd<1>                      2     3     FB4_6   49~  I/O     I/O     LOW  SLOW
    jd<14>                     2     3     FB4_10  51~  I/O     I/O     LOW  SLOW
    jd<7>                      2     3     FB4_11  48~  I/O     I/O     LOW  SLOW
    jd<8>                      2     3     FB4_12  52~  I/O     I/O     LOW  SLOW
    jd<6>                      2     3     FB4_14  50~  I/O     I/O     LOW  SLOW
    jd<9>                      2     3     FB4_15  56~  I/O     I/O     LOW  SLOW
    jd<13>                     2     3     FB4_17  57~  I/O     I/O     LOW  SLOW

    ** 5 Buried Nodes **

    Signal                     Total Total Loc     Pwr  Reg Init
    Name                       Pts   Inps          Mode State
    ireset0                    2     19    FB3_9   LOW  RESET
    bstate<2>                  2     17    FB3_13  LOW  RESET
    bstate<1>                  2     17    FB3_15  LOW  RESET
    bstate<0>                  2     17    FB3_18  LOW  RESET
    $OpTx$$OpTx$FX_DC$1_INV$9  1     2     FB4_18  LOW

    ** 3 Inputs **

    Signal                     Loc     Pin  Pin     Pin
    Name                               No.  Type    Use
    ja22                       FB3_9   27~  I/O     I
    jrw                        FB3_15  36~  I/O     I
    jrom1                      FB4_8   45~  I/O     I

    Legend:
    Pin No. - ~ - User Assigned
    **************************  Function Block Details  ************************
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X            - Signal used as input to the macrocell logic.
    Pin No.      - ~  - User Assigned
    *********************************** FB1  ***********************************
    Number of function block inputs used/remaining:               13/41
    Number of signals used by logic mapping into function block:  13
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    (unused)              0       0     0   5     FB1_1         (b)
    pd<10>                2       0     0   3     FB1_2   8~    I/O     I/O
    pd<14>                2       0     0   3     FB1_3   12~   I/O     I/O
    pd<15>                2       0     0   3     FB1_4   13~   I/O     I/O
    pd<11>                2       0     0   3     FB1_5   9~    I/O     I/O
    pd<12>                2       0     0   3     FB1_6   10~   I/O     I/O
    (unused)              0       0     0   5     FB1_7         (b)
    pd<13>                2       0     0   3     FB1_8   11~   I/O     I/O
    eza0                  2       0     0   3     FB1_9   15~   GCK/I/O O
    eza1                  3       0     0   2     FB1_10  18~   I/O     O
    (unused)              0       0     0   5     FB1_11  16    GCK/I/O
    (unused)              0       0     0   5     FB1_12  23    I/O
    (unused)              0       0     0   5     FB1_13        (b)
    (unused)              0       0     0   5     FB1_14  17    GCK/I/O
    ezwr31                3       0     0   2     FB1_15  19~   I/O     O
    (unused)              0       0     0   5     FB1_16        (b)
    ezrd30                3       0     0   2     FB1_17  20~   I/O     O
    (unused)              0       0     0   5     FB1_18        (b)

    Signals Used by Logic in Function Block
      1: $OpTx$$OpTx$FX_DC$1_INV$9   6: jrom1             10: jd<12>.PIN
      2: bstate<0>                   7: jrw               11: jd<13>.PIN
      3: bstate<1>                   8: jd<10>.PIN        12: jd<14>.PIN
      4: bstate<2>                   9: jd<11>.PIN        13: jd<15>.PIN
      5: ja22

    Signal                        1         2         3         4 FB
    Name                0----+----0----+----0----+----0----+----0 Inputs
    pd<10>               X....XXX................................ 4
    pd<14>               X....XX....X............................ 4
    pd<15>               X....XX.....X........................... 4
    pd<11>               X....XX.X............................... 4
    pd<12>               X....XX..X.............................. 4
    pd<13>               X....XX...X............................. 4
    eza0                 .X..XX.................................. 3
    eza1                 ..X.XXX................................. 4
    ezwr31               .XXXXXX....X............................ 7
    ezrd30               .XXXXXX................................. 6
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    *********************************** FB2  ***********************************
    Number of function block inputs used/remaining:               12/42
    Number of signals used by logic mapping into function block:  12
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    (unused)              0       0     0   5     FB2_1         (b)
    jd<10>                2       0     0   3     FB2_2   60~   I/O     I/O
    jd<2>                 2       0     0   3     FB2_3   58~   I/O     I/O
    jd<5>                 2       0     0   3     FB2_4   59~   I/O     I/O
    jd<12>                2       0     0   3     FB2_5   61~   I/O     I/O
    jd<3>                 2       0     0   3     FB2_6   62~   I/O     I/O
    (unused)              0       0     0   5     FB2_7         (b)
    jd<4>                 2       0     0   3     FB2_8   63~   I/O     I/O
    jd<11>                2       0     0   3     FB2_9   64~   GSR/I/O I/O
    (unused)              0       0     0   5     FB2_10  1     I/O
    (unused)              0       0     0   5     FB2_11  2     GTS/I/O
    pd<8>                 2       0     0   3     FB2_12  4~    I/O     I/O
    (unused)              0       0     0   5     FB2_13        (b)
    pd<9>                 2       0     0   3     FB2_14  5~    GTS/I/O I/O
    (unused)              0       0     0   5     FB2_15  6     I/O
    (unused)              0       0     0   5     FB2_16        (b)
    (unused)              0       0     0   5     FB2_17  7     I/O
    (unused)              0       0     0   5     FB2_18        (b)

    Signals Used by Logic in Function Block
      1: $OpTx$$OpTx$FX_DC$1_INV$9   5: pd<2>.PIN          9: jrom1
      2: pd<10>.PIN                  6: pd<3>.PIN         10: jrw
      3: pd<11>.PIN                  7: pd<4>.PIN         11: jd<8>.PIN
      4: pd<12>.PIN                  8: pd<5>.PIN         12: jd<9>.PIN

    Signal                        1         2         3         4 FB
    Name                0----+----0----+----0----+----0----+----0 Inputs
    jd<10>               .X......XX.............................. 3
    jd<2>                ....X...XX.............................. 3
    jd<5>                .......XXX.............................. 3
    jd<12>               ...X....XX.............................. 3
    jd<3>                .....X..XX.............................. 3
    jd<4>                ......X.XX.............................. 3
    jd<11>               ..X.....XX.............................. 3
    pd<8>                X.......XXX............................. 4
    pd<9>                X.......XX.X............................ 4
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    *********************************** FB3  ***********************************
    Number of function block inputs used/remaining:               22/32
    Number of signals used by logic mapping into function block:  22
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    (unused)              0       0     0   5     FB3_1         (b)
    (unused)              0       0     0   5     FB3_2   22    I/O
    pd<6>                 2       0     0   3     FB3_3   31~   I/O     I/O
    pd<7>                 2       0     0   3     FB3_4   32~   I/O     I/O
    (unused)              0       0     0   5     FB3_5   24    I/O
    pd<3>                 2       0     0   3     FB3_6   34~   I/O     I/O
    (unused)              0       0     0   5     FB3_7         (b)
    (unused)              0       0     0   5     FB3_8   25    I/O
    ireset0               2       0     0   3     FB3_9   27    I/O     I
    pd<2>                 2       0     0   3     FB3_10  39~   I/O     I/O
    pd<1>                 2       0     0   3     FB3_11  33~   I/O     I/O
    pd<0>                 2       0     0   3     FB3_12  40~   I/O     I/O
    bstate<2>             2       0     0   3     FB3_13        (b)     (b)
    pd<5>                 2       0     0   3     FB3_14  35~   I/O     I/O
    bstate<1>             2       0     0   3     FB3_15  36    I/O     I
    floe                  1       0     0   4     FB3_16  42~   I/O     O
    pd<4>                 2       0     0   3     FB3_17  38~   I/O     I/O
    bstate<0>             2       0     0   3     FB3_18        (b)     (b)

    Signals Used by Logic in Function Block
      1: $OpTx$$OpTx$FX_DC$1_INV$9   9: jd<11>.PIN        16: jd<3>.PIN
      2: bstate<1>                  10: jd<12>.PIN        17: jd<4>.PIN
      3: bstate<2>                  11: jd<13>.PIN        18: jd<5>.PIN
      4: ja22                       12: jd<14>.PIN        19: jd<6>.PIN
      5: jrom1                      13: jd<15>.PIN        20: jd<7>.PIN
      6: jrw                        14: jd<1>.PIN         21: jd<8>.PIN
      7: jd<0>.PIN                  15: jd<2>.PIN         22: jd<9>.PIN
      8: jd<10>.PIN

    Signal                        1         2         3         4 FB
    Name                0----+----0----+----0----+----0----+----0 Inputs
    pd<6>                X...XX............X..................... 4
    pd<7>                X...XX.............X.................... 4
    pd<3>                X...XX.........X........................ 4
    ireset0              ...XXXXXXXXXXXXXXXXXXX.................. 19
    pd<2>                X...XX........X......................... 4
    pd<1>                X...XX.......X.......................... 4
    pd<0>                X...XXX................................. 4
    bstate<2>            ...XXX.XXXXXX.XXXXXXXX.................. 17
    pd<5>                X...XX...........X...................... 4
    bstate<1>            ...XXX.XXXXXXX.XXXXXXX.................. 17
    floe                 .XXXXX.................................. 5
    pd<4>                X...XX..........X....................... 4
    bstate<0>            ...XXXXXXXXXX..XXXXXXX.................. 17
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    *********************************** FB4  ***********************************
    Number of function block inputs used/remaining:               17/37
    Number of signals used by logic mapping into function block:  17
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    (unused)              0       0     0   5     FB4_1         (b)
    preset                2       0     0   3     FB4_2   43~   I/O     O
    jd<15>                2       0     0   3     FB4_3   46~   I/O     I/O
    jd<0>                 2       0     0   3     FB4_4   47~   I/O     I/O
    flwe                  1       0     0   4     FB4_5   44~   I/O     O
    jd<1>                 2       0     0   3     FB4_6   49~   I/O     I/O
    (unused)              0       0     0   5     FB4_7         (b)
    (unused)              0       0     0   5     FB4_8   45    I/O     I
    (unused)              0       0     0   5     FB4_9         (b)
    jd<14>                2       0     0   3     FB4_10  51~   I/O     I/O
    jd<7>                 2       0     0   3     FB4_11  48~   I/O     I/O
    jd<8>                 2       0     0   3     FB4_12  52~   I/O     I/O
    (unused)              0       0     0   5     FB4_13        (b)
    jd<6>                 2       0     0   3     FB4_14  50~   I/O     I/O
    jd<9>                 2       0     0   3     FB4_15  56~   I/O     I/O
    (unused)              0       0     0   5     FB4_16        (b)
    jd<13>                2       0     0   3     FB4_17  57~   I/O     I/O
    $OpTx$$OpTx$FX_DC$1_INV$9
                          1       0     0   4     FB4_18        (b)     (b)

    Signals Used by Logic in Function Block
      1: bstate<0>          7: pd<13>.PIN        13: pd<8>.PIN
      2: bstate<1>          8: pd<14>.PIN        14: pd<9>.PIN
      3: bstate<2>          9: pd<15>.PIN        15: jrom1
      4: ireset0           10: pd<1>.PIN         16: jrw
      5: ja22              11: pd<6>.PIN         17: jd<14>.PIN
      6: pd<0>.PIN         12: pd<7>.PIN

    Signal                        1         2         3         4 FB
    Name                0----+----0----+----0----+----0----+----0 Inputs
    preset               ...XX.........XX........................ 4
    jd<15>               ........X.....XX........................ 3
    jd<0>                .....X........XX........................ 3
    flwe                 XXX.X.........XX........................ 6
    jd<1>                .........X....XX........................ 3
    jd<14>               .......X......XX........................ 3
    jd<7>                ...........X..XX........................ 3
    jd<8>                ............X.XX........................ 3
    jd<6>                ..........X...XX........................ 3
    jd<9>                .............XXX........................ 3
    jd<13>               ......X.......XX........................ 3
    $OpTx$$OpTx$FX_DC$1_INV$9
                         ....X...........X....................... 2
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    *******************************  Equations  ********************************

    ********** Mapped Logic **********

    $OpTx$$OpTx$FX_DC$1_INV$9 <= (ja22 AND jd(14).PIN);

    FDCPE_bstate0: FDCPE port map (bstate(0),'0','0',bstate_CLR(0),bstate_PRE(0));
    bstate_CLR(0) <= (NOT jd(9).PIN AND NOT jd(8).PIN AND NOT jd(7).PIN AND NOT jd(15).PIN AND
    	NOT jd(13).PIN AND NOT jd(12).PIN AND NOT jd(11).PIN AND NOT jd(10).PIN AND
    	NOT jd(5).PIN AND NOT jd(3).PIN AND ja22 AND NOT jd(6).PIN AND NOT jd(4).PIN AND NOT jrw AND
    	NOT jrom1 AND NOT jd(0).PIN AND jd(14).PIN);
    bstate_PRE(0) <= (NOT jd(9).PIN AND NOT jd(8).PIN AND NOT jd(7).PIN AND NOT jd(15).PIN AND
    	NOT jd(13).PIN AND NOT jd(12).PIN AND NOT jd(11).PIN AND NOT jd(10).PIN AND
    	NOT jd(5).PIN AND NOT jd(3).PIN AND ja22 AND NOT jd(6).PIN AND NOT jd(4).PIN AND NOT jrw AND
    	NOT jrom1 AND jd(0).PIN AND jd(14).PIN);

    FDCPE_bstate1: FDCPE port map (bstate(1),'0','0',bstate_CLR(1),bstate_PRE(1));
    bstate_CLR(1) <= (NOT jd(9).PIN AND NOT jd(8).PIN AND NOT jd(7).PIN AND NOT jd(15).PIN AND
    	NOT jd(13).PIN AND NOT jd(12).PIN AND NOT jd(11).PIN AND NOT jd(10).PIN AND
    	NOT jd(5).PIN AND NOT jd(3).PIN AND ja22 AND NOT jd(6).PIN AND NOT jd(4).PIN AND NOT jrw AND
    	NOT jd(1).PIN AND NOT jrom1 AND jd(14).PIN);
    bstate_PRE(1) <= (NOT jd(9).PIN AND NOT jd(8).PIN AND NOT jd(7).PIN AND NOT jd(15).PIN AND
    	NOT jd(13).PIN AND NOT jd(12).PIN AND NOT jd(11).PIN AND NOT jd(10).PIN AND
    	NOT jd(5).PIN AND NOT jd(3).PIN AND ja22 AND NOT jd(6).PIN AND NOT jd(4).PIN AND NOT jrw AND
    	jd(1).PIN AND NOT jrom1 AND jd(14).PIN);

    FDCPE_bstate2: FDCPE port map (bstate(2),'0','0',bstate_CLR(2),bstate_PRE(2));
    bstate_CLR(2) <= (NOT jd(9).PIN AND NOT jd(8).PIN AND NOT jd(7).PIN AND NOT jd(15).PIN AND
    	NOT jd(13).PIN AND NOT jd(12).PIN AND NOT jd(11).PIN AND NOT jd(10).PIN AND
    	NOT jd(5).PIN AND NOT jd(3).PIN AND NOT jd(2).PIN AND ja22 AND NOT jd(6).PIN AND
    	NOT jd(4).PIN AND NOT jrw AND NOT jrom1 AND jd(14).PIN);
    bstate_PRE(2) <= (NOT jd(9).PIN AND NOT jd(8).PIN AND NOT jd(7).PIN AND NOT jd(15).PIN AND
    	NOT jd(13).PIN AND NOT jd(12).PIN AND NOT jd(11).PIN AND NOT jd(10).PIN AND
    	NOT jd(5).PIN AND NOT jd(3).PIN AND jd(2).PIN AND ja22 AND NOT jd(6).PIN AND
    	NOT jd(4).PIN AND NOT jrw AND NOT jrom1 AND jd(14).PIN);

    eza0 <= ((NOT ja22 AND bstate(0))
    	OR (jrom1 AND bstate(0)));

    eza1 <= ((NOT ja22 AND bstate(1))
    	OR (jrom1 AND bstate(1))
    	OR (ja22 AND NOT jrw AND NOT jrom1));

    ezrd30 <= NOT (((ja22 AND jrw AND NOT jrom1)
    	OR (jrw AND NOT jrom1 AND bstate(2))
    	OR (bstate(2) AND bstate(1) AND NOT bstate(0))));

    ezwr31 <= NOT (((bstate(2) AND bstate(1) AND NOT bstate(0))
    	OR (ja22 AND NOT jrw AND NOT jrom1 AND NOT jd(14).PIN)
    	OR (NOT ja22 AND NOT jrw AND NOT jrom1 AND bstate(2))));

    floe <= NOT ((NOT ja22 AND jrw AND NOT jrom1 AND NOT bstate(2) AND NOT bstate(1)));

    flwe <= NOT ((NOT ja22 AND NOT jrw AND NOT jrom1 AND NOT bstate(2) AND NOT bstate(1) AND
    	NOT bstate(0)));

    FDCPE_ireset0: FDCPE port map (ireset0,'0','0',ireset0_CLR,ireset0_PRE);
    ireset0_CLR <= (jd(9).PIN AND jd(8).PIN AND jd(7).PIN AND NOT jd(15).PIN AND
    	jd(13).PIN AND jd(12).PIN AND jd(11).PIN AND NOT jd(10).PIN AND
    	jd(5).PIN AND jd(3).PIN AND jd(2).PIN AND ja22 AND NOT jd(6).PIN AND
    	NOT jd(4).PIN AND NOT jrw AND NOT jd(1).PIN AND NOT jrom1 AND NOT jd(0).PIN AND
    	jd(14).PIN);
    ireset0_PRE <= (jd(9).PIN AND jd(8).PIN AND jd(7).PIN AND NOT jd(15).PIN AND
    	jd(13).PIN AND jd(12).PIN AND jd(11).PIN AND NOT jd(10).PIN AND
    	jd(5).PIN AND jd(3).PIN AND jd(2).PIN AND ja22 AND NOT jd(6).PIN AND
    	NOT jd(4).PIN AND NOT jrw AND NOT jd(1).PIN AND NOT jrom1 AND jd(0).PIN AND
    	jd(14).PIN);

    jd_I(0) <= pd(0).PIN;
    jd(0) <= jd_I(0) when jd_OE(0) = '1' else 'Z';
    jd_OE(0) <= (jrw AND NOT jrom1);

    jd_I(1) <= pd(1).PIN;
    jd(1) <= jd_I(1) when jd_OE(1) = '1' else 'Z';
    jd_OE(1) <= (jrw AND NOT jrom1);

    jd_I(2) <= pd(2).PIN;
    jd(2) <= jd_I(2) when jd_OE(2) = '1' else 'Z';
    jd_OE(2) <= (jrw AND NOT jrom1);

    jd_I(3) <= pd(3).PIN;
    jd(3) <= jd_I(3) when jd_OE(3) = '1' else 'Z';
    jd_OE(3) <= (jrw AND NOT jrom1);

    jd_I(4) <= pd(4).PIN;
    jd(4) <= jd_I(4) when jd_OE(4) = '1' else 'Z';
    jd_OE(4) <= (jrw AND NOT jrom1);

    jd_I(5) <= pd(5).PIN;
    jd(5) <= jd_I(5) when jd_OE(5) = '1' else 'Z';
    jd_OE(5) <= (jrw AND NOT jrom1);

    jd_I(6) <= pd(6).PIN;
    jd(6) <= jd_I(6) when jd_OE(6) = '1' else 'Z';
    jd_OE(6) <= (jrw AND NOT jrom1);

    jd_I(7) <= pd(7).PIN;
    jd(7) <= jd_I(7) when jd_OE(7) = '1' else 'Z';
    jd_OE(7) <= (jrw AND NOT jrom1);

    jd_I(8) <= pd(8).PIN;
    jd(8) <= jd_I(8) when jd_OE(8) = '1' else 'Z';
    jd_OE(8) <= (jrw AND NOT jrom1);

    jd_I(9) <= pd(9).PIN;
    jd(9) <= jd_I(9) when jd_OE(9) = '1' else 'Z';
    jd_OE(9) <= (jrw AND NOT jrom1);

    jd_I(10) <= pd(10).PIN;
    jd(10) <= jd_I(10) when jd_OE(10) = '1' else 'Z';
    jd_OE(10) <= (jrw AND NOT jrom1);

    jd_I(11) <= pd(11).PIN;
    jd(11) <= jd_I(11) when jd_OE(11) = '1' else 'Z';
    jd_OE(11) <= (jrw AND NOT jrom1);

    jd_I(12) <= pd(12).PIN;
    jd(12) <= jd_I(12) when jd_OE(12) = '1' else 'Z';
    jd_OE(12) <= (jrw AND NOT jrom1);

    jd_I(13) <= pd(13).PIN;
    jd(13) <= jd_I(13) when jd_OE(13) = '1' else 'Z';
    jd_OE(13) <= (jrw AND NOT jrom1);

    jd_I(14) <= pd(14).PIN;
    jd(14) <= jd_I(14) when jd_OE(14) = '1' else 'Z';
    jd_OE(14) <= (jrw AND NOT jrom1);

    jd_I(15) <= pd(15).PIN;
    jd(15) <= jd_I(15) when jd_OE(15) = '1' else 'Z';
    jd_OE(15) <= (jrw AND NOT jrom1);

    pd_I(0) <= jd(0).PIN;
    pd(0) <= pd_I(0) when pd_OE(0) = '1' else 'Z';
    pd_OE(0) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);

    pd_I(1) <= jd(1).PIN;
    pd(1) <= pd_I(1) when pd_OE(1) = '1' else 'Z';
    pd_OE(1) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);

    pd_I(2) <= jd(2).PIN;
    pd(2) <= pd_I(2) when pd_OE(2) = '1' else 'Z';
    pd_OE(2) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);

    pd_I(3) <= jd(3).PIN;
    pd(3) <= pd_I(3) when pd_OE(3) = '1' else 'Z';
    pd_OE(3) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);

    pd_I(4) <= jd(4).PIN;
    pd(4) <= pd_I(4) when pd_OE(4) = '1' else 'Z';
    pd_OE(4) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);

    pd_I(5) <= jd(5).PIN;
    pd(5) <= pd_I(5) when pd_OE(5) = '1' else 'Z';
    pd_OE(5) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);

    pd_I(6) <= jd(6).PIN;
    pd(6) <= pd_I(6) when pd_OE(6) = '1' else 'Z';
    pd_OE(6) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);

    pd_I(7) <= jd(7).PIN;
    pd(7) <= pd_I(7) when pd_OE(7) = '1' else 'Z';
    pd_OE(7) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);

    pd_I(8) <= jd(8).PIN;
    pd(8) <= pd_I(8) when pd_OE(8) = '1' else 'Z';
    pd_OE(8) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);

    pd_I(9) <= jd(9).PIN;
    pd(9) <= pd_I(9) when pd_OE(9) = '1' else 'Z';
    pd_OE(9) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);

    pd_I(10) <= jd(10).PIN;
    pd(10) <= pd_I(10) when pd_OE(10) = '1' else 'Z';
    pd_OE(10) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);

    pd_I(11) <= jd(11).PIN;
    pd(11) <= pd_I(11) when pd_OE(11) = '1' else 'Z';
    pd_OE(11) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);

    pd_I(12) <= jd(12).PIN;
    pd(12) <= pd_I(12) when pd_OE(12) = '1' else 'Z';
    pd_OE(12) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);

    pd_I(13) <= jd(13).PIN;
    pd(13) <= pd_I(13) when pd_OE(13) = '1' else 'Z';
    pd_OE(13) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);

    pd_I(14) <= jd(14).PIN;
    pd(14) <= pd_I(14) when pd_OE(14) = '1' else 'Z';
    pd_OE(14) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);

    pd_I(15) <= jd(15).PIN;
    pd(15) <= pd_I(15) when pd_OE(15) = '1' else 'Z';
    pd_OE(15) <= (NOT jrw AND NOT jrom1 AND NOT $OpTx$$OpTx$FX_DC$1_INV$9);

    preset <= ((ireset0)
    	OR (NOT ja22 AND jrw AND NOT jrom1));

    Register Legend:
     FDCPE (Q,D,C,CLR,PRE,CE);
     FTCPE (Q,D,C,CLR,PRE,CE);
     LDCP  (Q,D,G,CLR,PRE);

    ******************************  Device Pin Out *****************************

    Device : XC9572XL-10-VQ64

       -----------------------------------------------
      /48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 \
     | 49                                           32 |
     | 50                                           31 |
     | 51                                           30 |
     | 52                                           29 |
     | 53                                           28 |
     | 54                                           27 |
     | 55                                           26 |
     | 56              XC9572XL-10-VQ64             25 |
     | 57                                           24 |
     | 58                                           23 |
     | 59                                           22 |
     | 60                                           21 |
     | 61                                           20 |
     | 62                                           19 |
     | 63                                           18 |
     | 64                                           17 |
     \ 1  2  3  4  5  6  7  8  9  10 11 12 13 14 15 16 /
       -----------------------------------------------

    Pin Signal                         Pin Signal
    No. Name                           No. Name
      1 KPR                              33 pd<1>
      2 KPR                              34 pd<3>
      3 VCC                              35 pd<5>
      4 pd<8>                            36 jrw
      5 pd<9>                            37 VCC
      6 KPR                              38 pd<4>
      7 KPR                              39 pd<2>
      8 pd<10>                           40 pd<0>
      9 pd<11>                           41 GND
     10 pd<12>                           42 floe
     11 pd<13>                           43 preset
     12 pd<14>                           44 flwe
     13 pd<15>                           45 jrom1
     14 GND                              46 jd<15>
     15 eza0                             47 jd<0>
     16 KPR                              48 jd<7>
     17 KPR                              49 jd<1>
     18 eza1                             50 jd<6>
     19 ezwr31                           51 jd<14>
     20 ezrd30                           52 jd<8>
     21 GND                              53 TDO
     22 KPR                              54 GND
     23 KPR                              55 VCC
     24 KPR                              56 jd<9>
     25 KPR                              57 jd<13>
     26 VCC                              58 jd<2>
     27 ja22                             59 jd<5>
     28 TDI                              60 jd<10>
     29 TMS                              61 jd<12>
     30 TCK                              62 jd<3>
     31 pd<6>                            63 jd<4>
     32 pd<7>                            64 jd<11>

    Legend :  NC  = Not Connected, unbonded pin
             PGND = Unused I/O configured as additional Ground pin
             TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
             KPR  = Unused I/O with weak keeper (leave unconnected)
             VCC  = Dedicated Power Pin
             GND  = Dedicated Ground Pin
             TDI  = Test Data In, JTAG pin
             TDO  = Test Data Out, JTAG pin
             TCK  = Test Clock, JTAG pin
             TMS  = Test Mode Select, JTAG pin
      PROHIBITED  = User reserved pin
    ****************************  Compiler Options  ****************************

    Following is a list of all global compiler options used by the fitter run.

    Device(s) Specified                         : xc9572xl-10-VQ64
    Optimization Method                         : SPEED
    Multi-Level Logic Optimization              : ON
    Ignore Timing Specifications                : OFF
    Default Register Power Up Value             : LOW
    Keep User Location Constraints              : ON
    What-You-See-Is-What-You-Get                : OFF
    Exhaustive Fitting                          : OFF
    Keep Unused Inputs                          : OFF
    Slew Rate                                   : FAST
    Power Mode                                  : LOW
    Ground on Unused IOs                        : OFF
    Set I/O Pin Termination                     : KEEPER
    Global Clock Optimization                   : ON
    Global Set/Reset Optimization               : ON
    Global Ouput Enable Optimization            : ON
    Input Limit                                 : 54
    Pterm Limit                                 : 25