					OCT. 19, 1987

Mike,
  Here is the circuit description for the UXE prototype. It
is organized by schematic pages. The U#'s referred to are as
shown on the schematics sent over the weekend. Points of
interest, especialy differences with the LSI design are
denoted *** CAPITALS ***.

PAGE 1

The oscillator can be anything you can get to work, although
a dip canned variety is the simplest. I would try 12 Mhz first.
You might want to add a divider to get the clocks for the MFP's
and SCC. The 244 buffer U102 is marked as a 'HC' but in the past
I have found that sometimes different types seem to work better
depending on layout and loading. Use whatever type makes the
best looking signal at the end of the wire.

U105 is a priority encoder but since the CPU already prioritizes
the interrupts, only the 8-3 encode function is of interest.
*** IF AN INTERRUPT OCCURS THAT IS MASKED BY THE CPU, THE PRIORITY
ENCODER U105 WILL BLOCK LOWER PRIOITY INTERRUPTS. *** If this
gives software a problem, I can modify the corresponding circuit
in the LSI. 

The reset circuit shown is just for power-on reset XPOR. If XPOR
is active then XRES is also active but not vice versa. If you
add a reset button to U107 it will generate a power-on reset
which wipes RAM. You might want to add a reset button which
only generates XRES which should preserve RAM.

U104 is there to provide address strobes with the assertion delayed
by one, two, or three clocks. As the circuit stands now, the MCU
uses the address strobe with one clock delay, and everything else
uses the two clock delay. If you have any problems with slow
decoders, the strobe with three clock delays could be substituted
to give more address set-up time.

The PAL U106 is a simple decode of the CPU address space. The only
things in CPU address space currently used are the FPU coprocessor
and the interrupt acknowledge.

The FPU is hooked up straight out of the Motorola book. I shown
pull-ups on the open drain lines but you might want to add some
for the address and data.

PAGE 2

The PAL U202 is a simple circuit to generate the ROM chip select
and the delayed acknowledge. It should generate the acknowledge
three clocks after the select for a total of about four and a
half clocks access. 200-250 ns ROMs should be fine. The ROM
like most of the IO is treated as an eight bit port responding
only DSACK0.

U204 and U205 form the refresh timer. It is a count-down timer
with the time constant wired to B4h. The refresh request XRFRQ
should be generated every 180 clocks which is 15 us with a 12 Mhz
clock. If you have to slow down the clock you might need to change
the time constant although I have found that the 15 us refresh time
on most DRAMs is very conservative.  *** IN THE LSI MCU, THE REFRESH
TIME CONSTANT WILL BE PROGRAMMABLE BY WRITING TO A ROM LOACATION
WHOSE ADDRESS IS THE DESIRED TIME CONSTANT. THIS WILL BE NECESSARY
DURING COLD START. THE TIME CONSTANT WILL SET TO 8 ON POWER-UP
RESET TO ENSURE PROPER DRAM START-UP. ***

PAL U212 decodes the function codes and upper address. ROM is the
lower 4 meg of system space. XIO is a 4 meg block of system space
at the top of the first 16 meg. RAM is the second 16 meg block
of system and user space.

	ROM	00000000 - 0003FFFF	system prog./data
	IO	00FF0000 - 00FFFFFF		"
	RAM	01000000 - 01FFFFFF	sys/user prog/data

The signal XCIIN is generated for ROM and IO space to inhibit
caching. U210 is an attempt to synchronize this signal to the
clock. XCIIN and XSTERM are synchronous inputs to the CPU and
must not change during a window around the rising edges of the
clock.

PAL U218 decodes the byte selects. All bytes are always selected
for reads but only the appropriate bytes on writes. The byte
selects are used to enable the appropriate CAS's and by the
decoder on page 5.

U222-U224 form a 9 bit up counter to provide the refresh address.

The S153's are the DRAM address mux. XROW selects the row/column
and REFEN selects the refresh address.

PAGE 3

This is the guts of the MCU control circuit. The upper half is the
timing chain for refresh. U301-U302 latch the refresh request. When
the address strobe goes high, indicating that no bus cycle is in
progress, U310 sets at the next falling edge of the clock generating
REFEN. One half clock later, U311 sets causing XRAS to go low. One
clock later U309 sets. This resets U301-U302 removing the J input
to U310 and it activates U310's K input. Thus U310 will reset on
the next falling edge of the clock. U311's K input is also activated
so it will reset on the next rising edge of the clock. U304's output
will go low during the clock cycle between U311 reseting and U309
reseting. U307-U308 delay this another two clocks to give enough
RAS precharge time before the next RAM cycle is allowed to start.

U323-U329 also latch the refresh request but the output is used to
inhibit RAM cycles while refresh is on. Once set, this latch will
be reset by the output from U308 when the refresh is done and RAS
has been high long enough.

The bottom row is the timing chain for normal RAM cycles. U330
will activate U335's J input when RAM is selected, address strobe
goes low, and no refresh cycle is in progress. U335 will set on
a rising edge of the clock generating RAS. One half clock later
U336 will switch row to column. On the next rising edge U337
will set enabling CAS. With both U330 and U337 set, the next
rising edge of the clock will set U334. U334 setting clears U335
removing RAS. U336 and U337 will then reset on successive clock
edges except that with normal timing U337 will get reset by
address strobe rising before it would via its D input. During
normal RAM cycles U327 and U314 outputs should remain high so
XCASEN and XSTM (sterm) will follow U337. Also note that XWE
follow XRAS during write cycles.

This stuff in the middle was added to try and support burst
cycles. On burst cycles, XCBRQ will follow XAS. Burst cycles
are allways 32 bit read cycles. When address strobe and burst
request are both low, the latch U314-U315 will reset. This
interrupts the normal path for XSTM. U322 will set on the
first falling edge of the clock. This will hold U334 set
blocking the normal reset path to U335. Also U325 will begin
to toggle on falling edges of the clock. The normal RAM
timing chain will proceed as in normal RAM cycles up to
the point where the U335 reset path is blocked. Thus RAS
remains active and U337 remains set. The toggling of U325
is used generate XSTM and a half clock delayed vesion
(via U326) is fed to U327 which selectivly inhibits the
CASEN. The result is that the DRAM should operate in nybble
mode. When XCBRQ goes back high, U22 will reset stopping
U325 and allowing U334 to operate terminating the cycle
normaly. When address strobe goes high U314-U315 sets
restoring the conditions for normal RAM cycles.

PAGE 4

A bank of DRAM.

PAGE 5

PAL U528 decodes the IO space. The gates around it combine the
various byte selects and what-not to produce the read and write
strobes for the registers and chip selects for the periferals.
The control register U533-U534 is a 2 bit read/write register
decoded as LSB's of a 32 bit port. *** THE PROTOTYPE ONLY
DRIVES THE LOW BYTE AND ALL 8 BITS EXIST EVEN THOUGH ONLY 0-1
ARE CONNECTED TO ANYTHING. THE LSI WILL DRIVE ALL 32 BITS
ON READS AND BITS 2-31 MAY OR MAY NOT BE DEFINED. SOFTWARE
SHOULD USE ONLY BITS 0-1, WRITE ONLY TO THE LOW BYTE, AND
WRITE THE UNSED BITS IN THAT LOW BYTE TO 0'S. ***
I may use some of the other bits for testing or expansion.
The counter selects (XRCNTR, XWC--) access the 32 DMA address
counter on page 6. XRLTCH accesses the read only SCSI data
latch on page 6. The MFP's and SCSI chip are connected as
8 bit ports to the CPU. The MFP's require only simple chip
selects and generate their own acknowledge. The SCSI chip
gets its select in the form of dedicated read and write
strobes and U543 is used to generate an acknowledge after
a one clock delay.

PAL U515 forms a state machine to generate the timing to access
the RTC. U518-U525 provide a multiplexed address/data bus to the
RTC which is operated using the INTEL like timing mode.

	SCSI		00FF0000-00FF0003	2 IMAGES R/W
	DMA ADDR	00FF0004-00FF0007	32 BIT R/W
	CONTROL		00FF0008-00FF000B	SEE TEXT
	DATA LATCH	00FF000C-00FF000F	32 BIT R/W
			00FF0010-00FF001F	RESERVED
	MFP1		00FF0020-00FF003F	MC68901
	MFP2		00FF0040-00FF005F
	SCC		00FF0060-00FF0063	85C30
			00FF0064-00FF00FF	RESERVED
	RTC		00FF0100-00FF01FF	MC146818
			00FF0200-00FFFFFF	RESERVED

PAGE 6

The first thing you might notice about this page is how full it
is. Over on the right is the DMA address counter. This counter
is loaded with the DMA base address and its contents are driven
to the address bus during DMA. The counter is a 32 bit read/write
register except that bits 0-1 are slightly different as I hope
to explain. U614, U625, and U626 generate an equivalent RCO
output for the first stage (U618) of the counter. Notice only
two bits in the first stage are used.

Lower center is the data latch. Here the 8 bit data from the SCSI
chip is latched to 32 bits for the memory or the 32 bit memory
data is latch to be fed to the SCSI chip 8 bits at a time.

At the upper left, U601, U603, U602, and U604 duplicate part of
a function from the CPU. The acknowledge signals are each sampled
on the appropriate edges of the clock, the end result being that
the signal ACK should go high after the rising edge of bus cycle
state 4 (see Motorola data for 68030 or 68020). ACK is used as an
input to the state machine in PAL7 (it didn't get numbered??) and
by the register decoder to terminate write cycles early (to get
more data hold time).

Just below is the circuit to generate the bus request. When the
internal signal RQ is active and the CPU is not already granting
the bus, U609-U611 make U613 J high. On the next rising edge of the
clock, U613 sets generating bus request. U615 blocks propagation
of the bus grant. When BGA from the PAL7 state machine goes
active, U613 is allowed to reset removing bus request and allowing
bus grant to pass to XBGO.

PAL7 generates the timing signals when the SCSI DMA is on the bus.
To start the state machine, RQ, XAS, XSTM, XDS0, XDS1, XBGO, and XBGACK
must be high and XBG must be low. Once started the state machine
will genrate the timing signals to transfer data on the bus.
XASO and XDSO become XAS and XDS respectivly. XDB is delayed one
half clock by U606 then turns on the bus drivers. BGA enables
XBGACK and indicates that the DMA circuit is master of the bus.
XASO delayed by U621 provides the clock to increment the address
counter.

U637 is clocked each time the SCSI chip is acknowledged via XSBACK.
When DMAA0 and DMAA1 are both one, indicating that the data transfers
are crossing a double word boundary, U637 sets causing a request
to get the next double word.

U638 is held reset until EN goes high. It sets at the end of the
first bus cycle when the address is incremented. The signal FIRST
is just a flag to distinguish the first bus transfer from the rest.

When the SCSI chip request a data transfer with SBREQ, U624 will
clock out the acknowledge straight away unless a RQ is pending or
XASO is low (a bus cycle is in progress). Thus the SCSI chip can
go as fast as it wants for 4 bytes then it must wait until the
DMA circuit disposes or replenishes the data.

U646 and U651 both store the low order two bits of the DMA address
when the counter is loaded. U651 is clocked by the ackowledge to
the SCSI chip and serves to generate the byte selects for the
data latch. U646 is just a latch to hold the initial bits.

During the first bus cycle, U644 is set by FIRST to gate out
the initial address bits and size selects so that the bus cycle
request the proper amount of data be transfered. For the remainder
of the transfers the low address bits and size selects are forced
to zero indicating double word transfers. This is done so that
transfers to the memory from SCSI don't change bytes below the
base address. During transfers from memory this really doesn't
matter but it doesn't hurt. When the base address is a double
word boundary (a1=a0=0) it doesn't matter either.

_____________________
DIR = 1  CPU to SCSI

U632 is clocked when EN goes high causing RQ to be generated right
away. This is to get the first data into the latch for the SCSI
chip. Once XASO occurs during this first cycle, U632 is reset.

The outputs from U652 decoded from DMAA0 and DMAA1 select which
of the four bytes in the data latch to send to the SCSI chip.

U666 outputs a gating signal which asserts one half clock after
XASO or in state 2. U657 delays the ACK signal one half clock
and thus provides a gating signal to indicate the beginning of
state 5 when the CPU would latch data. These gating signals
are combined in U658 to generate the latch signal to latch
the memory data into the SCSI data latch.

_____________________
DIR = 0   SCSI to CPU

Going this direction, the data gating signal coming out of U666
is used to enable data from the SCSI data latch out to the memory.
The SCSI data is latched into the data latch by combining the SCSI
acknowledge with the byte selects coming out of U652. 

Note also that the read latch signal XRLTCH will also enable latch
data to the CPU.

_________________________

The way I envisioned DMA working is that the CPU writes directly
to the SCSI chip to set things up. The CPU writes the base address
and sets the DIR bit in the control register. *** SOFTWARE SHOULD
SET THE DIR AND EN BITS OF THE CONTROL REGISTER IN SEPARATE WRITES
TO PREVENT POSSIBLE RACE CONDITIONS. *** The CPU sets the EN bit
then goes on to other things. When SCSI is done, it generates an
interrupt. When servicing that interrpt, the CPU must read any
left over data in the latch (SCSI to memory only), then set the EN
bit back low.

PAGE 7

Just a simple state machine to generate the inexorably slow timing
needed for the SCC. Mostly multiclock delays of everything. The
timing should be fine for normal stuff but might be a little tight
for interrupt ackowledge cycles. Get the CMOS 85C30 8Mhz minimum
10 Mhz better.


P.S. I'm sending a new page 6. Just a minor correction.

					John
